Central processing units (CPU) often include one or more levels of embedded cache memory. These cache memories duplicate frequently-accessed data stored in main-memory thereby speeding memory access time. As computing power increases, so does the size of CPU cache. But access speeds suffer as memory cache size increases. Often, processor cache architectures utilize static random access memory (SRAM) cells.
In mobile devices and other applications, conserving power is important. One currently-known conservation method places the device into a standby-mode. While in standby-mode, SRAM can be brought into a low-power mode sustained by a voltage level lower than a normal-operation voltage without losing stored data bits. When the SRAM is subsequently accessed, it is brought back up to a normal-power mode.